The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

英伟达GPU时钟集团正在寻找一名优秀的高级ASIC验证工程师加入该团队。该团队负责制作GPU时钟的所有方面。该团队与前端设计团队合作，以了解芯片的时钟要求。我们还了解后端团队对时钟施加的物理限制。GPU时钟组设计、设计和验证时钟RTL。时钟RTL的复杂性增加了许多倍，以支持我们的功能，这些功能为我们的产品线提供了动力，从消费者图形到自动驾驶汽车，以及不断增长的人工智能领域。

What you’ll be doing:

岗位职责：

Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc.

开发用于验证高速时钟逻辑的测试计划、测试和验证基础设施，包括许多方面：功能、DFT、电路、功率、物理设计约束等。

You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery.

您需要了解时钟RTL的功能、测试和计时模式，并在RTL交付之前验证这些模式。

You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies.

您将与其他验证工程师合作，提供创造性的解决方案，以跨各种验证层次重用编程序列。

Build verification environment using SV/UVM methodology

使用SV/UVM方法构建验证环境

Build reusable functional models, monitors, checkers and scoreboards

构建可重用的功能模型、监视器、跳棋和记分牌

Drive coverage driven verification closure

驱动覆盖率驱动的验证结束

Work with architects, designers and post-silicon teams.

与建筑师、设计师和后硅团队合作。

Methodology development for above tasks.

上述任务的方法开发。

What we need to see:

招聘条件：

BS / MS in electrical / computer engineering and related.

电气/计算机工程及相关专业理学学士/硕士。

1+ years ASIC verification experience.

1年以上ASIC验证经验。

Unit/Sub-system/SOC level verification experience

单元/子系统/SOC级验证经验

Strong programming skills in Perl/Python and C/C++, Verilog or SV.

精通Perl/Python和C/C++、Verilog或SV编程。

Your proven knowledge/experience with industry standard verification tools for simulation and debug

您对用于模拟和调试的行业标准验证工具的成熟知识/经验

Confirmed debugging and strong analytical skills.

确认调试和强大的分析能力。

Familiar with verification methodology, tools and flow.

熟悉验证方法、工具和流程。

Understand ASIC design and timing.

了解ASIC设计和时序。

Validated excellent interpersonal skills.

验证了优秀的人际交往技能。

Ways to stand out from the crowd:

从人群中脱颖而出的方法：

Excellent analytical and problem-solving skills.

优秀的分析和解决问题的能力。

Fluent English (both written and spoken) and excellent communication skills.

流利的英语（书面和口语）和优秀的沟通技巧。

Good team work spirit, easy to cooperate with team members.

良好的团队合作精神，易于与团队成员合作。

DFT knowledge is plus.

有DFT知识者优先。

Strong prior knowledge/experience in Clocking/Resets verification is plus.

有较强的时钟/重置验证经验者优先。

Your shown experience in verification methodologies like UVM is plus.

您在验证方法（如UVM）方面的经验更佳。

Leadership and planning experience is plus.

有领导和规划经验者优先。

来源：CAREERS AT NVIDIA (myworkdayjobs.com)